High-speed networks are continually evolving. The evolution includes a continuing advancement in the operational speed of the networks. The network implementation of choice that has emerged is Ethernet networks physically connected over unshielded twisted pair wiring. Ethernet in its 10BASE-T form is one of the most prevalent high speed LANs (local area network) for providing connectivity between personal computers, workstations and servers.
High-speed LAN technologies include 100BASE-T (Fast Ethernet) and 1000BASE-T (Gigabit Ethernet). Fast Ethernet technology has provided a smooth evolution from 10 Megabits per second (Mbps) performance of 10BASE-T to the 100 Mbps performance of 100BASE-T. Gigabit Ethernet provides 1 Gigabit per second (Gbps) bandwidth with essentially the simplicity of Ethernet. There is a desire to increase operating performance of Ethernet to even greater data rates.
FIG. 1 shows a block diagram of an Ethernet transceiver pair communicating over a bi-directional transmission channel, according to the prior art. The transceiver pair includes a first transceiver 100 and a second transceiver 105. The first transceiver 100 includes a transmitter section 110 that receives digital data for transmission over a transmission channel 135. The first transceiver 100 also includes a receiver section 120 that receives data.
The transceiver includes a digital to analog converter (DAC) for transmission, and an analog to digital converter (ADC) for reception. The hybrid circuit 130 is designed to reduce the level the transmit signal present in the receive signal path. The transmitter section 110 and the receiver section 120 are connected to a common twisted pair causing some of the transmission signals of the transmitter section 110 to be coupled into the receive signals of the receiver section 120. The coupled signal can be referred to as an “echo” signal.
The hybrid circuit 140 of the second transceiver 105 operates in the same manner as the hybrid circuit 130 of the first transceiver 100. The transmitter section 150 and the receiver section 160 of the second transceiver 105 operate in the same manner as the transmitter section 110 and receiver section 120 of the first transceiver 100.
An implementation of high speed Ethernet networks includes simultaneous, full bandwidth transmission, in both directions (termed full duplex), within a selected frequency band. When configured to transmit in full duplex mode, Ethernet line cards are generally required to have transmitter and receiver sections of an Ethernet transceiver connected to each other in a parallel configuration to allow both the transmitter and receiver sections to be connected to the same twisted wiring pair for each of four pairs.
FIG. 2 shows several Ethernet twisted pair LAN connections 212, 214, 216, 218 in parallel. The first connection 212 is between a first transmitter 115a (S1A) and first receiver 125a (R1A), and a second transmitter 115b (S1B) and a second receiver 125b (R1B). The second connection 214 is between a third transmitter 135a (S2A) and third receiver 145a (R2A), and a fourth transmitter 135b (S2B) and a fourth receiver 145b (R2B). The third connection 216 is between a fifth transmitter 155a (S3A) and fifth receiver 165a (R3A), and a sixth transmitter 155b (S3B) and a sixth receiver 165b (R3B). The fourth connection 218 is between a seventh transmitter 175a (S4A) and seventh receiver 185a (R4A), and an eighth transmitter 175b (S4B) and an eighth receiver 185b (R4B).
The twisted pair LAN connections 212, 214, 216, 218 are located physically proximate, and interference between the twisted pairs 212, 214, 216, 218 is caused by interactions between signals of the twisted pair LAN connections 212, 214, 216, 218. Interference can also be caused by connectors of the twisted pair LAN connections. The interference is in the form of far end cross-talk (FEXT) and near-end cross-talk (NEXT). NEXT is caused by interference due to signals generated at the near-end of a neighboring twisted pair connection. For example, NEXT interference includes the transmitter signals S1A, S3A, S4A of transmitters 115a, 155a, 175a interfering with receiver signal R2A of receiver 145a. FEXT is caused by interference due to signals generated at the far-end of a neighboring twisted pair connection. For example, FEXT interference includes the transmitter signals S1B, S3B, S4B of transmitters 115b, 155b, 175b interfering with receiver signal R2A of receiver 145a. Other interference includes the echo signal. For example, the echo signal includes interference the signal S2A of transmitter 135a interfering with the receiver signal R2A of receiver 145a. Additional interference includes inter-symbol interference (ISI). ISI is self-interference of the transmit signal S2B at the input R2A of the receiver 145a. Other interference can include alien signal interference. Alien signal interference generally includes interference due to other Ethernet twisted pair LAN connections of cables that may be proximate to the twisted pair cable of the signal of interest.
Present Ethernet technology can include time domain processing of digital signal streams for minimization of signal interference. As the data frequencies of the digital signal streams increases, the electronic hardware required to implement the time domain processing increases dramatically.
Digital filtering is generally used to reduce the signal interference of Ethernet signals. Digital communications systems use filtering for many functions. These functions include adjacent and co-channel interference rejection, equalization, echo canceling and cross-talk canceling. Finite impulse response (FIR) filtering can be utilized to reduce signal interference. FIR filtering can require complex circuit implementations. For example, if an FIR filter has a length P (samples), P multiply and accumulate (MAC) operations are required per filtered output signal. High performance communication systems (this generally refers to high throughput systems) the length of the FIR filters can be much greater. The electronic circuitry required to implement high performance FIR filters can become very large, requiring greater cost and higher power dissipation. High performance filters can require lengths (P) of 50-1000 taps in which each tap operates on a sampled signal delayed by one (or fraction of one) symbol period from the previous tap. Additionally, high performance systems can require several filters.
A Gigabit Ethernet system can require echo, NEXT and FEXT cancellation and equalization. Additionally, Ethernet systems generally include 4 adjacent twisted pair connections per communication link, requiring NEXT and FEXT cancellation for each of the pairs. The twisted pairs of a communication link can additionally alien NEXT cancellation due to interference received from other twisted pair communication links.
It is desirable to have an apparatus and method for a high throughput transceiver that provides for pre-processing and post-processing of digital signal streams for minimization of interference of Ethernet LAN signals. It is desirable to minimize the latency of the pre-processing and post-processing. The processing should require a minimal amount of electronic hardware, and dissipate a minimal amount of power. Alternatively, the processing should enable higher data transmission rates, and allow for longer transmission channels using comparable hardware and power dissipation.